Semiconductor capacitor structure and method for manufacturing the same

ABSTRACT

In one embodiment, a semiconductor device comprises a base and a tapered wall formed on the base. The wall has a midline and also has an inner sidewall and an outer sidewall. The inner sidewall and the outer sidewall are substantially symmetrical with each other in relation to the midline. Thus, the reliability of the semiconductor capacitor structure can be improved and the throughput can be increased. Also, further scaling down of semiconductor devices can be facilitated with the principles of the present invention.

BACKGROUND OF THE INVENTION

This application claims the priority of Korean Patent Application No.2003-0056009, filed on Aug. 13, 2003, in the Korean IntellectualProperty Office, the contents of which are incorporated herein in theirentirety by reference.

1. Field of the Invention

The present invention relates to semiconductor devices and, moreparticularly, to semiconductor capacitor structures and methods formanufacturing the same.

2. Description of the Related Art

The driving capability of semiconductor devices such as dynamic randomaccess memory (DRAM) is determined by the capacitance of capacitors,which generally consist of a capacitor dielectric layer sandwichedbetween two capacitor electrodes. The capacitance is largely determinedby the total surface area of the electrodes and the distance between theelectrodes as determined by the thickness of the capacitor dielectriclayer. Therefore, many attempts have been made to increase thecapacitance by increasing the effective surface area of the capacitorelectrodes.

Unfortunately, however, as semiconductor devices become more highlyintegrated, the area allocated for forming capacitors within the devicestypically becomes reduced. In other words, as integration densityincreases, the width of capacitors narrows, and it becomes moredifficult to obtain the desired capacitance levels.

Fabrication technologies have been developed to increase the height of acapacitor electrode or storage node, to increase the effective surfacearea thereof and to retain a desirable cell capacitance of the unitcell. For example, a storage node can be formed in a concave orcylindrical shape having a height of more than 1 μm.

Unfortunately, as the height of the storage node increases, the area ofthe storage node decreases due to the increasingly sloped profile of thestorage node formation hole. This leads to an increasingly unstable andunreliable capacitor structure. In particular, a phenomenon such as“stiction” or “leaning” of storage nodes can occur, especially if theheight of the storage nodes is above 15,000 nm. These problems areillustrated, for example, FIGS. 1A and 1B. The stiction phenomenon istypically caused by the surface tension of a liquid drop remainingbetween the ends of adjacent storage node electrodes during a dryingprocess performed before a cleaning process. The leaning phenomenon iscaused by a difference in the coefficients of thermal expansion (CTE)between an etch stop nitride layer and storage nodes during thermalcycling.

To improve the stability of the capacitor structures, the width of thebottom portion of the storage node should be increased and a sufficientdistance between the adjacent storage nodes need to be ensured. In thisrespect, a minimum space critical dimension (CD) has been defined torepresent a desired distance between adjacent storage nodes in adiagonal direction. Increasing this minimum space CD reduces thelikelihood that the storage nodes will not fall in the event that thereis leaning of storage nodes.

However, as illustrated in FIGS. 2A-2B, obtaining the sufficientdistance between the storage nodes has become more difficult as thedevice sizes become scaled down. In particular, it is difficult toincrease the width W of the bottom portion of the storage nodes withoutdecreasing the distance B between the adjacent storage nodes. Inparticular, as the width W of the storage node bottom portion increasesto W′ by an amount A (See FIG. 2B), the distance B between the storagenodes inevitably decreases to B′ by a proportionate amount.

It is, therefore, difficult to form a reliable capacitor structurewithout decreasing the storage node bottom portion while avoidingconventional problems such as stiction or leaning of storage nodes.

SUMMARY OF THE INVENTION

In one embodiment of the present invention, a semiconductor capacitorlower electrode comprises a base; and a tapered wall formed on the base.The wall has a midline. The wall has an inner sidewall and an outersidewall. The inner sidewall and the outer sidewall are substantiallysymmetrical with each other in relation to the midline.

In one aspect, the wall is stepwise tapered. In another aspect, the wallis tapered gradually without a step.

In accordance with another embodiment of the present invention, a methodfor forming a semiconductor device comprises: forming an interlayerinsulating layer on a semiconductor substrate, the interlayer insulatinglayer having a conductive pad therein; forming an etch stop layer on theinterlayer insulating layer; forming a first sacrificial layer on theetch stop layer; forming a first storage node opening in the firstsacrificial layer; depositing a conductive layer on the firstsacrificial layer and on the sidewalls and the bottom of the opening;forming a second sacrificial layer on the conductive layer; planarizingthe resulting structure until the top surface of the first sacrificiallayer is exposed; partially removing an upper portion of the first andsecond sacrificial layers to expose a sidewall portion of the conductivelayer; thinning the exposed sidewall portion; and removing the remainingportion of the first and second sacrificial layers.

Thus, the reliability of the semiconductor capacitor structure can beimproved and the throughput can be increased. Also, further scaling downof semiconductor devices can be facilitated with the principles of thepresent invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and additional objects and advantages of the present inventionwill become more readily apparent through the following detaileddescription of preferred embodiments, made with reference to theattached drawings in which:

FIGS. 1A-1B are a plan and a perspective view, respectively, of acapacitor lower electrode illustrating conventional problems of stictionand leaning of storage nodes;

FIG. 2 is a cross-sectional view of a structure to form a conventionalsemiconductor device illustrating the problems of the prior art;

FIGS. 3 through 14 are cross-sectional views illustrating a method ofmanufacturing a capacitor according to an embodiment of the embodimentof the present invention; and

FIG. 15 is a cross-sectional view of a capacitor lower electrode of asemiconductor device according to yet another embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully with reference tothe accompanying drawings, in which preferred embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as being limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete and will fully conveythe concept of the invention to those skilled in the art. In thedrawings, the shape of elements is exaggerated for clarity, and the samereference numerals in different drawings represent the same element.

Referring to FIG. 3, to form a semiconductor device having a storagenode according to one embodiment of the present invention, a firstinsulating layer 10 having a contact plug 20 formed therein is formed ona semiconductor substrate 11. The first insulating layer 10 can beformed of a dielectric material such as oxide. The substrate 11 may be asemiconductor wafer such as a silicon wafer or a predetermined materiallayer formed thereon. Although not shown, a lower structure that mayinclude source/drain regions and gate electrodes can be formed on thesemiconductor substrate 11 to form a transistor or a memory cell. Thecontact plug 20 is electrically connected to a storage node be formedthereon, for example, using conventional techniques. The contact plug 20is also electrically connected to active regions of the semiconductorsubstrate 11. Although not shown, the contact plug 20 may be connectedto the active regions via a contact pad, as is known to one skilled inthe art. The first insulating layer 10 may be planarized.

Next, an etch stop layer 30 and a second insulating layer 40 aresequentially formed on the first insulating layer pattern 10, such as isknown in the art. The etch stop layer 30 may, for example, be formed ofa material such as silicon nitride having an etch selectivity withrespect to the second insulating layer 40 to serve as an end pointduring a subsequent etching lift-off process to remove the secondinsulating layer 40. The second insulating layer 40 may be formed ofoxide having a thickness between about 3,000 to 20,000 angstroms using alow-pressure chemical vapor deposition (LPCVD) process, for example. Thesecond insulating layer 40 can be a single layer of plasma-enhancedtetraethylorthosilicate (PE-TEOS) or a multilayer including the PE-TEOSlayer.

Referring to FIG. 4, a photoresist 50 is then preferably formed on thesecond insulating layer 40.

Referring to FIG. 5, the photoresist 50 can be patterned to form aphotoresist pattern 50′ having an opening 51 overlying the contact plug20.

Referring to FIG. 6, the second insulating layer 40 and the etch stoplayer 30 are subsequently etched using the photoresist pattern 50′ as anetching mask, thereby forming a second insulating layer pattern 70 andan etch stop layer pattern 60, through which a storage node contact hole80 extends.

Turning to FIG. 7, the photoresist pattern 50′ is then removed and aconductive layer 90 is conformally deposited over the second insulatinglayer pattern 70, but does not completely fill the storage node hole 80.Typically, in the prior art, the conductive layer 90 is formed to athickness of about 400 angstroms. However, according to one embodimentof the present invention, the thickness of the conductive layer 90 maybe about 600 angstroms. Thus, the width of the storage node bottomportion can be increased, thereby improving the stability of thecapacitor structure, as will explained further below. The conductivelayer 90 is preferably formed of a material such as a doped polysilicon,a metal such as W, Pt, Ru, and Ir, a conductive metal nitride such asTiN, TaN, and WN, and a conductive metal oxide such as RuO₂ and IrO₂,and any combination thereof. Then, a third insulating layer or asacrificial layer 100 is preferably formed to a thickness such that thesecond insulating layer pattern 70 is completely covered.

Referring to FIG. 8, the resulting structure is preferably planarized toform separated storage nodes 110 using conventional planarizationtechniques such as chemical mechanical polishing (CMP). During theplanarization process, the top of the conductive layer 90 and the secondand third insulating layers 70, 100 are planarized to form separatedstorage nodes 110.

Referring to FIG. 9, the planarized second and third insulating layers70, 100 are partially removed in a vertical direction. Preferably, anetch selectivity ratio for the second and third insulating layers 70,100 and the storage nodes 110 is approximately 1000:1. Thus, during thisprocess, the storage nodes 110 are preferably substantially leftunetched.

In particular, the planarized second and third insulating layers 70, 100can be partially removed through a chemical dry etching process. Thechemical dry etching process preferably uses a gas phase without aplasma for etching. For example, a vaporized wet etchant such asanhydrous HF vapor plus H₂O (gas) can be used. Because the chemical dryetching process can be performed without using a plasma, etching damageto the substrate surface can be reduced. Isoprophyl Alcohol (IPA), analcohol group having CH₃OH, or carboxylic acid having CH₃COOH can beused as a catalyst. The temperature of the substrate 11 may beapproximately 0˜60° C. Further, the flow rate of anhydrous HF may beapproximately 100˜2000 sccm/sec. Also, the flow rate of IPA may beapproximately 50˜200 sccm/sec.

Alternatively, the planarized second and third insulating layers 70, 100can be etched or removed through a wet etching process using BOE(Buffered Oxide Etchant, i.e., HF+NH₄F). This is possible due to morestable storage node structure constructed according to the principles ofthe present invention.

Referring to FIG. 10, thinning of the exposed sidewall portion of thestorage node 110 is illustrated. In other words, inner and outersidewalls 17, 19 of partially exposed storage node 110 are thenpreferably partially etched in a horizontal direction. For example, theinner and outer sidewalls 17, 19 of the partially exposed storage node110 are both etched to a width of, for example, approximately 40angstroms. An etch selectivity ratio for the storage nodes 110 and thesecond insulating layer pattern 70 (or the third insulating layer 100)is preferably greater than or equal to approximately 10:1. As in thevertical etching described above, the side walls of the partiallyexposed storage nodes 110 can be partially etched through a chemical dryetching process. The chemical dry etching process may use a gas phaseetchant such as CF₄+O₂. The temperature of the substrate 11 may beapproximately 0˜60° C. The power may be approximately 100 W˜600 W. Thepressure may be approximately 10˜50 Pa. The flow rate of CF₄ may beapproximately 30˜80 sccm/sec. The flow rate of O₂ may be approximately150˜300 sccm/sec.

Alternatively, the side walls 17, 19 of partially exposed storage node110 may be partially etched in a horizontal direction through a wetetching process using SC1.

Either the chemical dry etching or wet etching can be used in either orboth of the vertical or horizontal etching process. If the same etchingmethod is used to perform both the vertical or horizontal etchingprocess, the vertical and horizontal etching processes can be performedin situ.

One skilled in the art, however, will appreciate that the presentinvention is not limited to above process conditions, and that the aboveprocess conditions represent one of many possible sets of processconditions that can be used to form the stable capacitor structure ofthe present invention.

Referring to FIG. 11, the second insulating layer pattern 70 and thethird insulating layer 100 are partially further removed again in avertical direction without substantially etching the storage node 110using a method similar to that described in connection with FIG. 9.

Referring to FIG. 12, the inner and outer side walls of the partiallyexposed storage nodes 110 are partially etched further again in ahorizontal direction using a method similar to that described withreference to FIG. 10.

The number of the above horizontal and vertical etching steps can bedetermined depending on the particular application. For example, morehorizontal and vertical etchings can be added or even reduced. In thisembodiment, the number of steps formed on sidewalls of the storage nodes110 is determined by the number of the horizontal and vertical etchingsteps.

Referring to FIG. 13, the remaining second insulating layer pattern 70and the third insulating layer 100 are substantially completely removedusing an etchant such as BOE.

After removing the insulating layers 70, 100, a phosphine annealingprocess may be performed to improve the surface characteristics of thestorage node 110.

Thus, according to the foregoing embodiment of the present invention,the width of the bottom portion of the storage node 110 can be increasedby an amount “x”, as indicated in FIG. 13, compared to the prior artcapacitor structure represented by the dotted lines. The amount x ispreferably in the range of 10 nm to 40 nm. The width of the bottomportion of the conventional storage node is represented by the letter W,while W′ indicates the width of the bottom portion of the storage node110 according to the above-described embodiment of the presentinvention. Preferably, the width W is about 3,200 angstroms and thewidth W′ is about 4,000 angstroms. Also, the angle between the outersidewalls 19 and the top surface of the storage node 110 may be closerto 90°, for example, 90±2° than that of the prior art structure. Thus,the distance “y” between the adjacent storage nodes 110 and the width ofthe bottom portion of the storage node can be substantially increased,as compared with the prior art capacitor structure. For this reason, thestability of the capacitor structure can be substantially increased,thereby decreasing the conventional problems such as stiction or leaningof storage nodes 110.

Referring to FIG. 14, a capacitor dielectric layer 120, formed, forexample, of a conventional capacitor dielectric, is formed on thestorage node (capacitor lower electrode) 110. Then, a capacitor upperelectrode 130 is formed on the capacitor dielectric layer 120 tocomplete a capacitor 40. As in the lower electrode 110, the upperelectrode 130 may be formed of a material selected from the groupconsisting of a doped polysilicon, a metal such as W, Pt, Ru, and Ir, aconductive metal nitride such as TiN, TaN, and WN, and a conductivemetal oxide such as RuO₂ and IrO₂, and any combination thereof. However,the upper electrode 14 and the capacitor lower electrode 12 may beformed of different materials.

Accordingly, the capacitor 40 fabricated by the processes describedabove comprises a storage node 110 having a base 12 (or a bottomportion). The capacitor 40 further includes a tapered wall 14 formed onthe base 12.

According to one aspect of the present invention, the wall 14 preferablyhas an upper portion 32 and a lower portion 34. The width of the upperportion 32 is at least 200 angstroms and the width of the lower portionis at least 400 angstroms. Thus, the lower portion 34 preferably has agreater width than the upper portion 32. The lower portion may be aportion of the wall 14 immediately below the upper portion 32 or theupper portion may be a portion of the wall 14 immediately above thelower portion 34.

Although it is not illustrated in the drawings, corners of the top endportion of the storage node 110 are preferably rounded off to prevent adevice failure.

In one aspect, the wall 14 can be viewed as having an inner sidewall 17and an outer sidewall 19. The wall 14 may be seen to have a midline 18,which is a center line connecting the mid points between the upper andthe inner sidewalls 17, 19. The midline 18 is a virtual line drawn toillustrate concepts of the present invention. The inner sidewall 17 andthe outer sidewall 19 are preferably substantially symmetrical with eachother in relation to the midline 18.

In yet another aspect, the wall 14 may be stepwise tapered. Inparticular, the wall 14 has a first step 38 formed on the inner sidewall17 and a second step 36 formed on the outer sidewall 19. The first andsecond steps 36, 38 may be substantially symmetrical in relation to themidline 18.

According to still another aspect of the present invention, the outersidewall 19 of the wall 14 forms an approximately 90 degree angle withrespect to the plane 13 of the base 12 or the top surface of the storagenode 110, thus increasing the distance between the storage nodes 110.The outer sidewall 19 of the wall 14, however, may have a slightlypositive slope with respect to the plane of the base.

FIG. 15 illustrates an alternative embodiment. Referring to FIG. 15, thewall 14 may be tapered gradually without a step. In other words, thewidth of the storage node 110 is gradually reduced from the bottom tothe top of the wall 14. Although the process illustrated in FIGS. 3-14are particularly directed to forming a wall that is stepwise tapered,one skilled in the art will understand how to form the wall that istapered gradually without a step. For example, the structure shown inFIG. 15 can be formed using an etchant that can perform both thevertical and horizontal etching concurrently. The etch selectivity ratiocan be chosen to perform both the horizontal and vertical etchingprocesses.

In either embodiment, the base 12 and the wall 14 preferably form astorage node of one cylinder stack (OCS) capacitor. The storage node orthe wall 14 may be substantially square, circle, or oval in shape whenviewed in plan view.

In conclusion, according to various embodiments of the presentinvention, minimum space CD can be more easily controlled compared withthe conventional capacitor structure. Also, the bottom portion of thestorage node 110 is wider than the top portion of the storage node 110or the bottom portion of the conventional storage node. Further, becausethe angle between the outer sidewalls 19 and the top surface of thestorage node 110 or the plane 13 of the base 12 can be made closer to90° than that of the prior art structure, the distance between thestorage nodes 110 can increased.

For these reasons, the stability of the capacitor structure can besubstantially increased, thereby decreasing the conventional problemssuch as a stiction or leaning phenomenon. And the minimum space CD canbe further reduced to, for example, less than about 40 nm as comparedwith about 60 nm of the conventional storage node structure.

Thus, the reliability of the semiconductor capacitor structure can beimproved and the throughput can be increased. Also, further scaling downof semiconductor devices can be facilitated with the principles of thepresent invention.

While the principles of the present invention have been shown anddescribed with reference to the particular embodiments described herein,it will be understood by those skilled in the art that various changesin form and detail may be made thereto without departing from the spiritand scope of the invention, as covered by the following claims.

1. A semiconductor device, comprising: a base; and a tapered wall formedon the base, the wall having a midline, wherein the wall has an innersidewall and an outer sidewall, wherein the inner sidewall and the outersidewall are substantially symmetrical with each other in relation tothe midline.
 2. The semiconductor device of claim 1, wherein the wall isstepwise tapered.
 3. The semiconductor device of claim 1, wherein thewall is tapered gradually without a step.
 4. A semiconductor device,comprising: a base; and a wall formed on the base, wherein the wall isstepwise tapered.
 5. The semiconductor device of claim 4, wherein thewall has an upper portion and a lower portion, and wherein the lowerportion of the wall has a greater width than the upper portion of thewall.
 6. The semiconductor device of claim 4, wherein the base and wallform a storage node of one cylinder stack (OCS) capacitor.
 7. Thesemiconductor device of claim 4, wherein the wall is substantiallysquare, circle, or oval when viewed in plan view.
 8. The semiconductordevice of claim 4, wherein the wall has an inner sidewall and an outersidewall, wherein the wall has a first step formed on the inner sidewalland a second step formed on the outer sidewall, and wherein the firstand second steps are substantially symmetrical.
 9. The semiconductordevice of claim 8, wherein the outer sidewall of the wall forms anapproximately 90 degree angle with the plane of the base.
 10. Thesemiconductor device of claim 9, wherein the outer sidewall has apositive slope with respect to the plane of the base.
 11. Thesemiconductor device of claim 4, wherein corners of the top end portionof the wall is rounded off.
 12. A semiconductor device, comprising: asemiconductor substrate; an interlayer insulating layer formed on thesemiconductor substrate, the interlayer insulating layer having acontact pad formed therein; and a capacitor lower electrode electricallyconnected to the contact pad, the capacitor lower electrode comprising:a base; and a tapered wall formed on the base, the wall having amidline, wherein the wall has an inner sidewall and an outer sidewall,wherein the inner sidewall and the outer sidewall are substantiallysymmetrical with each other in relation to the midline.
 13. Thesemiconductor device of claim 12, wherein the wall is stepwise tapered.14. The semiconductor device of claim 12, wherein the wall is taperedgradually without a step.
 15. A method for forming a semiconductordevice, the method comprising: forming an interlayer insulating layer ona semiconductor substrate, the interlayer insulating layer having aconductive pad therein; forming an etch stop layer on the interlayerinsulating layer; forming a first sacrificial layer on the etch stoplayer; forming a storage node opening in the first sacrificial layer;depositing a conductive layer on the first sacrificial layer and on thesidewalls and the bottom of the opening; forming a second sacrificiallayer on the conductive layer; planarizing the resulting structure untilthe top surface of the first sacrificial layer is exposed; partiallyremoving an upper portion of the first and second sacrificial layers toexpose a sidewall portion of the conductive layer; thinning the exposedsidewall portion; and removing the remaining portion of the first andsecond sacrificial layers.
 16. The method of claim 15, wherein partiallyremoving an upper portion and thinning the exposed sidewall portion arerepeated one or more times.
 17. The method of claim 15, whereinpartially removing an upper portion of the first and second sacrificiallayers comprises chemical dry etching.
 18. The method of claim 17,wherein an etch selectivity ratio for the first and second sacrificiallayers and the conductive layer is approximately 1000:1.
 19. The methodof claim 17, wherein the chemical dry etching uses a gas phase without aplasma for etching.
 20. The method of claim 19, wherein the gas phasecomprises a vaporized wet etchant.
 21. The method of claim 19, whereinthe gas phase comprises anhydrous HF vapor plus H₂O (gas).
 22. Themethod of claim 21, wherein Isoprophyl Alcohol (IPA), an alcohol grouphaving CH₃OH, or carboxylic acid having CH₃COOH is used as a catalyst.23. The method of claim 21, wherein a temperature of the substrate isapproximately 0˜60° C.; a flow rate of anhydrous HF is approximately100˜2000 sccm/sec; and a flow rate of IPA is approximately 50˜200sccm/sec.
 24. The method of claim 15, wherein partially removing anupper portion of the first and second sacrificial layers comprises wetetching.
 25. The method of claim 24, wherein the etchant comprises BOE26. The method of claim 15, wherein thinning comprises chemical dryetching.
 27. The method of claim 26, wherein the chemical dry etchinguses a gas phase comprising CF₄+O₂.
 28. The method of claim 27, whereinthe temperature of the substrate is approximately 0˜60° C.; a power isapproximately 100 W˜600 W; a pressure is approximately 10˜50 Pa; a flowrate of CF₄ is approximately 30˜80 sccm/sec; and a flow rate of O₂ isapproximately 150˜300 sccm/sec.
 29. The method of claim 15, whereinthinning comprises wet etching.
 30. The method of claim 29, wherein thewet etching comprising using SC1.
 31. The method of claim 15, whereinthinning comprises currently etching the wall on both sides thereof. 32.The method of claim 15, wherein thinning comprises forming a first andsecond step on an inner and outer side sidewall of the wall,respectively, and wherein the first and second steps are substantiallysymmetrical.
 33. The method of claim 15, wherein an etch selectivityratio for the conductive layer and the first and second sacrificiallayers during the thinning is greater than equal to approximately 10:1.34. The method of claim 15, further comprising: forming a dielectriclayer over the conductive layer; and forming an upper electrode on thedielectric layer.
 35. A method for forming a semiconductor device, themethod comprising: forming an interlayer insulating layer on asemiconductor substrate, the interlayer insulating layer having aconductive pad therein; forming an etch stop layer on the interlayerinsulating layer; forming a first sacrificial layer on the etch stoplayer; forming a storage node opening in the first sacrificial layer;depositing a conductive layer on the first sacrificial layer and on thesidewalls and the bottom of the opening; forming a second sacrificiallayer on the conductive layer; planarizing the resulting structure untilthe top surface of the first sacrificial layer is exposed; partiallyremoving the first and second sacrificial layers in a vertical directionto expose inner and outer sidewalls of the planarized conductive layer;partially removing the inner and outer sidewalls of the partiallyexposed conductive layer in a horizontal direction; and removing theremaining portion of the first and second sacrificial layers.
 36. Themethod of claim 35, wherein the inner and outer sidewalls of thepartially exposed conductive layer are both etched to a width ofapproximately 10˜40 angstroms.
 37. The method of claim 35, whereinpartially removing the first and second sacrificial layers; andpartially removing the inner and outer sidewalls of the partiallyexposed conductive layer are performed in situ.
 38. The method of claim35, wherein partially removing comprises using a gas phase comprisinganhydrous HF vapor and H₂O gas.
 39. The method of claim 35, whereinpartially removing comprises using a gas phase comprising CF₄+O₂. 40.The method of claim 35, wherein partially removing an upper portion andpartially etching the inner and outer sidewalls of the partially exposedconductive layer are repeated one or more times.
 41. The method of claim35, further comprising: forming a dielectric layer over the conductivelayer; and forming an upper electrode on the dielectric layer.
 42. Amethod forming a semiconductor device, the method comprising: forming aninterlayer insulating layer on a semiconductor substrate, the interlayerinsulating layer having a conductive pad therein; forming an etch stoplayer on the interlayer insulating layer; forming a first sacrificiallayer on the etch stop layer; forming a first storage node opening inthe first sacrificial layer; depositing a conductive layer on the firstsacrificial layer and on the sidewalls and the bottom of the opening;forming a second sacrificial layer on the conductive layer; planarizingthe resulting structure until the top surface of the first sacrificiallayer is exposed to form a storage node; concurrently performingvertical and horizontal etching on the resulting structure such that awidth of the storage node is gradually reduced from a bottom to a top ofthe storage node; and removing the remaining portion of the first andsecond sacrificial layers.
 43. The method of claim 42, wherein thestorage node is tapered gradually without a step.
 44. The method ofclaim 42, further comprising: forming a dielectric layer over thestorage node; and forming an upper electrode on the dielectric layer.